Back Side Power Chips

Currently chips or IC's, vastly and broadly important worldwide across many economies, especially for internet, and World Wide Web functionality, are currently made on the frontside of the silicon wafers. After photolithography etches the transistors by the billion into the front of the wafer, metals layers of copper interconnects are layered on to power and move data to and from the transistors. The entire front side action layers of the wafer are flipped when connecting the chip to its package, flip chip, such that if you remove the heatsink from your CPU or GPU, you will be seeing the silicon backside or support structure layer of highly purified silicon with a metallic blue appearance after you solvent wipe the heat sink compound off the chip which normally transfer heat from the chip the CPU or GPU cooling heatsink and fan or liquid cooling system.

In smartphone imaging sensors, Sony BSI or backside illuminated CMOS was a huge step forward in terms of low light performance and power efficiency improvement. By putting the wires an transistors behind the optical sensors, more light can hit each pixel sensor, improving imaging performance, especially on smaller CMOS chips that are made by the billion. 

Backside power delivery in chips an emerging technology because there is not enough space for data and power on the frontside with the transistors heading to the 1.6nm scale node and smaller. So BSP or backside power means data IO will still happen on the front side, while power will happen on the backside. In this way the transistors will be sandwiched between a power layer on the bottom and a data layer on the top. This will still work for flip chips, and can be adapted to existing chip fab production processing with almost no serious modification to equipment, as BSP more a design level change in how power and data will be separated as top and bottom layers encapsulating the transistor layer. 

https://youtu.be/hyZlQY2xmWQ?si=wifAOYuDv_-uCqKc

Intel 20A and 18A process nodes make the fine data wires so densely packed that signal noise becomes a problem with power and data wires co-located, so moving the power to the back of the IC and Data connections to the front, improves power efficiency, in chip data flow rates, IO rates, reliability, reducing chip temperatures, improves signal clarity or reducing noise, and overall improving performance & scalability all the way down to atom level detail chipsets in the 20 year horizon. 

Health tracking devices like Apple Watch or Gear from Samsung, requires the most power efficient TSMC tight small SOC with very tightly optimized software, such that we will see these product classes push market pressures for BSP technology on deep EUV ASML lithography applied broadly with continual improvement and ongoing optimizations. In this way computation technology forms feedback loops of progress that enables ongoing process optimization and improvement to chip power efficiency and performance. Artificial intelligence narrow domain optimization GAN processing can already help Intel, Boeing and other big players like Alphabet Inc or Qualcomm achieve chips with amazing improvements. 

Aging power grigs and not enough fiber in the ground means network IO can radically improve. Wired and fiber are way better than wifeless because of space wind and particle noise from sunlight, ions in the atmosphere and busy overlapping RF noise across the FCC spectrum, from gamma to the edge of light. 

Energy storage + renewable energy resources and new nuclear means broad decarbonization through ongoing industrialization. We have not even used but a tiny thin layer of the mantel of Earth, most human activity in just the top few miles. The oceans are poorly explore and space trash a growing problem. We have solutions to all the problems, if we have the boldness to apply technology: 42